FIG. 1 shows a conventional system. This system includes a DSP 1, a LSI 2 and a frequency dividing circuit 3. The DSP 1 and the LSI 2 are connected through an address bus 4, a data bus 5 and a control bus 6.
The address bus 4 is used for transmitting an address signal AD from the DSP 1 to the LSI 2. The data bus 5 is used to transmit writing data from the DSP 1 to the LSI 2. The control bus 6 is used to transmit a writing control signal /WE and a reading control signal /RE from the DSP 1 to the LSI 2. The writing control signal /WE instructs data-writing operation, in which “/” means that the signal is active at a low level “L”. The reading control signal /RE instructs data-reading operation.
The frequency dividing circuit 3 divides a clock signal CLK, supplied from the DSP 1 by N to supply a frequency-divided clock signal CK signal to the LSI 2. Generally, the DSP 1 has a higher performance and the clock signal CLK has a frequency of higher than several 100 MHz. On the other hand, the LSI 2 operates a lower speed and could not operate based on the high frequency clock signal CLK. For that reason, the frequency of the clock signal CLK is divided by the frequency dividing circuit 3 to provide a low frequency clock signal CK, to be supplied to the LSI 2.
FIG. 2 is a timing chart showing writing and reading operations of the system shown in FIG. 1. The frequency dividing circuit 3 divides the clock signal CLK by four (dividing ratio N=4).
A clock signal CLK outputted from the DSP 1 is divided in frequency by four at the frequency dividing circuit 3 to provide a frequency-divided clock signal CK. Four of frequency-divided clock signals CK1, CK2, CK3 and CK4, having different phases, are selectively used.
For writing data DT supplied from the DSP 1 into the LSI 2, an address signal AD is supplied from the DSP 1 to the address bus 4 at a timing of t1 in FIG. 2, in which the clock signal CLK is turned to high or rising up. At a timing t2, in which the clock signal CLK is turned to high, the data DT to be written are supplied to the data bus 5. And at the same time, a low level “L” of the writing control signal /WE is supplied to the control bus 6.
After the writing control signal /WE is turned to low “L”, the data DT on the data bus 5 are supplied to the LSI 2 at a first rising point of the frequency-divided clock signal CK, supplied from the frequency dividing circuit 3.
As described above, the frequency dividing circuit 3 supplies one of four frequency-divided clock signals CK1–CK4. However, it is not known which one of the clock signals CK1–CK4 is actually supplied to the LSI 2. Therefore, the data DT can be written into the LSI at a timing of t3, t4, t5 or t6. At the latest timing of t6, the writing control signal /WE is turned to high “H”.
After that, at a timing t7 in which the clock signal CLK is turned to high, both the address signal AD and data DT are stopped being supplied. For reading data DT from the LSI 2, an address signal AD is supplied to the address bus 4 at a timing t11, in which the clock signal CLK is turned to high. At a timing t12, in which the clock signal CLK is turned to high, a reading control signal /RE is supplied to the control bus 6.
On the other hand, after the writing control signal /WE, supplied from the DSP 1, is turned to low “L”, the data DT on the data bus 5 is supplied to the LSI 2 at a timing in which the frequency-divided clock signal CK is turned to high.
As described above, it is not known which one of the clock signals CK1–CK4 is actually supplied to the LSI 2. Therefore, the data DT can be written into the LSI at a timing of t3, t4, t5 or t6. At the latest timing of t6, the writing control signal /WE is turned to high “H”.
At a timing “t7”, in which the clock signal CLK is turned to high “H”, both of the address signal AD and the data DT are stopped being supplied. For reading data DT from LSI 2, an address signal AD is supplied from the DSP 1 to the address bus 4 at a timing “t11” shown in FIG. 2 in which the clock signal CLK is turned to high “H”. At the next rising point of the clock signal CLK at a timing “t12”, a low level “L” of a reading control signal /RE is supplied to the control bus 6.
On the other hand, after the reading control signal /RE, supplied from the DSP 1, is turned to low “L”, the data DT designated by the address signal AD is supplied onto the data bus 5 at a timing in which the frequency-divided clock signal CK is turned to high “H”. It is not known which one of the clock signals CK1–CK4 is actually supplied to the LSI 2. Therefore, the data DT can be supplied on to the data bus 5 at a timing of one of “t13,” “t14,” “t15” and “t16”. At the latest timing of “t16”, the reading control signal /RE is turned to high “H”.
At a timing “t17”, in which the clock signal CLK is turned to high “H”, the address signal AD is stopped being supplied.
However, according to the above described conventional system, the following disadvantages arise:
The frequency dividing circuit 3 produces N (four) different phases of frequency-divided clock signal CKi, and it is not known which one of them is to be actually used at the DSP 1 side. Therefore, in order to read and write data DT, it is required to use the latest timing clock.
As a result, in the case where the frequency dividing circuit 3 divides a frequency of the base clock CLK by “N”, “N+1” clocks would be required to perform each reading and writing operation. For example, for the dividing ratio N=16, seventeen clocks are required to perform each reading and writing operation. Such adjustment of timing is carried out at the DSP 1 by program-controlling timings of supplying the reading control signal /RE and the writing control signal /WE, that is a waiting time. However, according to an ordinary DSP, the maximum period of time that can be controlled by a program is limited. Therefore, if a frequency dividing circuit 3 has a large dividing ratio, reading and writing operations could not be carried out.